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Scan Logic For Circuit Designs With Latches And Flip-Flops
Scan Logic For Circuit Designs With Latches And Flip-Flops
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机译:带有锁存器和触发器的电路设计的扫描逻辑
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摘要
Embodiments of the present disclosure may include a system for scanning a circuit, the embodiments including flip-flops, latches interleaved between the flip-flops, multiplexers configured to propagate scan data between the flip-flops and latches, and scan logic configured to control the multiplexers to load test data into the flip-flops and latches. A first pair of latches are interleaved between a first pair of flip-flops.
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