TRANSISTOR STRUCTURES HAVING REDUCED ELECTRICAL FIELD AT THE GATE OXIDE AND METHODS FOR MAKING SAME

摘要

A transistor device having reduced electrical field at the gate oxide interface is disclosed. In one embodiment, the transistor device comprises a gate, a source, and a drain, wherein the gate is at least partially in contact with a gate oxide. The transistor device has a P+ region within a JFET region of the transistor device in order to reduce an electrical field on the gate oxide.