The invention relates to a time-triggered computer system 800 that involves [i] a Processor (801) that has been designed to run in one of two or more pre-determined system modes, in each of which it will execute one or more tasks according to a predetermined task schedule; and [ii] a System-Mode Data Store (802) that contains information about the next system mode that the system is required to operate in; and [iii] a Processor Reset Mechanism (803) that will reset the Processor when it is necessary to change the system mode; and [iv] a Processor Configuration Mechanism (804) that is designed to configure the Processor in accordance with the required system mode after a Processor reset, using information stored in the System-Mode Data Store, and [v] a Task-Timing Data Store (805), that contains information about the Task WCET Limit and/or Task BCET Limit for one or more tasks that are executed by the Processor, and [vi] a Task-Execution-Time Monitoring Mechanism (806) that is designed to monitor the execution time of tasks that are executed by the Processor and take corrective action, by means of the Processor Reset Mechanism (803) and the Processor Configuration Mechanism 804, if the task breaches its pre-determined Task WCET Limit or Task BCET Limit.
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