Dual-port SRAM timing control circuit which can reduce the operational power consumption of SRAM without affecting the read reliability

摘要

A dual-port SRAM timing control circuit, with three NMOS transistors connected in series respectively between ground and nodes of the two bit lines to which the cell structure corresponds. The gates of the NMOS transistors are connected to a corresponding wordline, a pulse signal and a timing control signal, respectively. The each pulse signals are formed by a corresponding clock signal inputted into a first pulse generator, respectively. An address signal, after passing through an address latch, is inputted into an address comparator for comparison, with the address comparison result outputted to a timing control signal generator; and the pulse signal, after undergoing an AND operation, is inputted into the timing control signal generator, with a timing control signal outputted. When the two address signals are the same, the address comparison result is 1; when the two address signals are not the same, the address comparison result is 0; when the AND result of the two pulse signals is 0, the timing control signal is 1; when the AND result of the two pulse signals is 1, the timing control signal is an inverting signal of the address comparison result. The present invention can reduce the operational power consumption of SRAM without affecting the read reliability.