Comparison of Replica Bitline Technique and Chain Delay Technique as Read Timing Control for Low-Power Asynchronous SRAM

摘要

Two 8kbit SRAMs, one using a replica technique and the other using an inverter chain delay as timing control for word line and sense amplifiers, are simulated in 90nm CMOS technology. The stability of both SRAMs against process variations and operating conditions are compared. Results show that the bit line swing is more stable against process variations and operating conditions for the replica bit line based design. However, for the sense timing, no significant advantage is observed for the replicabitline based design due to the size of the bit line. The replicabitline technique can have significant advantage against inverter chain delay for large bit line heights.