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Method of CMOS manufacturing utilizing multi-layer epitaxial hardmask films for improved epi profile
Method of CMOS manufacturing utilizing multi-layer epitaxial hardmask films for improved epi profile
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机译:利用多层外延硬掩模膜的CMOS制造方法以改善外延轮廓
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摘要
An integrated circuit containing PMOS transistors may be formed by forming a dual layer hard mask. A first layer of the hard mask is halogen-containing silicon nitride formed using a halogenated silane reagent. A second layer of the hard mask is silicon nitride formed on the first layer using halogen-free reagents. After source/drain cavities are etched in the PMOS transistors, a pre-epitaxial bake with hydrogen is performed. After SiGe epitaxial source/drain regions are formed, the hard mask is removed.
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