首页>
外国专利>
Multi-layer charge trap silicon nitride/oxynitride layer engineering with interface region control
Multi-layer charge trap silicon nitride/oxynitride layer engineering with interface region control
展开▼
机译:带界面区域控制的多层电荷陷阱氮化硅/氮氧化物层工程
展开▼
页面导航
摘要
著录项
相似文献
摘要
A non-volatile memory semiconductor device comprising a semiconductor substrate having a channel and a gate stack above the channel. The gate stack comprises a tunnel layer adjacent to the channel, a charge trapping layer above the tunnel layer, a charge blocking layer above the charge trapping layer, a control gate above the charge blocking layer, and an intentionally incorporated interface region between the charge trapping layer and the charge blocking layer. The charge trapping layer comprises a compound including silicon and nitrogen, the charge blocking layer contains an oxide of a charge blocking component, and the interface region comprises a compound including silicon, nitrogen and the charge blocking component. The tunnel layer may comprise up to three tunnel sub-layers, the charge trapping layer may comprise two trapping sub-layers, and the charge blocking layer may comprise up to five blocking sub-layers. Various gate stack formation techniques can be employed.
展开▼