首页> 外国专利> 3D STATIC RAM CORE CELL HAVING VERTICALLY STACKED STRUCTURE, AND STATIC RAM CORE CELL ASSEMBLY COMPRISING SAME

3D STATIC RAM CORE CELL HAVING VERTICALLY STACKED STRUCTURE, AND STATIC RAM CORE CELL ASSEMBLY COMPRISING SAME

机译:具有垂直堆叠结构的3D静态RAM核心单元,以及包含相同组件的静态RAM核心单元

摘要

Provided is a 3D static RAM core cell having a vertically stacked structure, the static RAM core cell comprising six thin film transistors, each of which has a gate electrode, a source electrode, and a drain electrode, the static RAM core cell comprising: two thin film transistors for switching, which are each connected to a bit line and a word line and select the recording and reading of data; and four thin film transistors for data storage, which are connected to a power supply voltage (Vdd) or a ground voltage (Vss) and allow the recording and reading of data, the static RAM core cell comprising: a first transistor layer comprising two thin film transistors selected from among the six thin film transistors; a second transistor layer which is positioned on the first transistor layer and comprises two thin film transistors selected from among the other four thin film transistors; and a third transistor layer which is positioned on the second transistor layer and comprises the other two thin film transistors, wherein the one or more kinds of electrodes of the first transistor layer and the one or more kinds of electrodes of the second transistor layer are electrically connected, and the one or more kinds of electrodes of the second transistor layer and the one or more kinds of electrodes of the third transistor layer are electrically connected. As such, the 3D static RAM core cell having a vertically stacked structure according to the present invention allows a complex patterning process for forming different types of organic transistors to be omitted during the manufacture of memory elements by disposing the same type of organic transistors on the same plane and vertically stacking same and can improve the degree of integration of a semiconductor circuit by reducing the area taken up by the memory elements.
机译:提供一种具有垂直堆叠结构的3D静态RAM核心单元,该静态RAM核心单元包括六个薄膜晶体管,每个薄膜晶体管具有栅电极,源电极和漏电极,该静态RAM核心单元包括:两个用于开关的薄膜晶体管,分别连接到位线和字线,并选择记录和读取数据;以及用于数据存储的四个薄膜晶体管,其连接到电源电压(Vdd)或地电压(Vss)并允许记录和读取数据,静态RAM核心单元包括:第一晶体管层,其包括两个薄层。从六个薄膜晶体管中选择的薄膜晶体管;第二晶体管层位于第一晶体管层上,并且包括从其他四个薄膜晶体管中选择的两个薄膜晶体管;第三晶体管层,其位于第二晶体管层上并包括另外两个薄膜晶体管,其中,第一晶体管层的一种或多种电极和第二晶体管层的一种或多种电极是电学的连接,并且第二晶体管层的一种或多种电极和第三晶体管层的一种或多种电极电连接。这样,根据本发明的具有垂直堆叠结构的3D静态RAM核心单元允许通过在存储元件的制造过程中通过将相同类型的有机晶体管布置在衬底上而省略用于形成不同类型的有机晶体管的复杂图案化工艺。平面和垂直堆叠相同,并且可以通过减小存储元件占用的面积来提高半导体电路的集成度。

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