首页>
外国专利>
3D STATIC RAM CORE CELL HAVING VERTICALLY STACKED STRUCTURE, AND STATIC RAM CORE CELL ASSEMBLY COMPRISING SAME
3D STATIC RAM CORE CELL HAVING VERTICALLY STACKED STRUCTURE, AND STATIC RAM CORE CELL ASSEMBLY COMPRISING SAME
展开▼
机译:具有垂直堆叠结构的3D静态RAM核心单元,以及包含相同组件的静态RAM核心单元
展开▼
页面导航
摘要
著录项
相似文献
摘要
Provided is a 3D static RAM core cell having a vertically stacked structure, the static RAM core cell comprising six thin film transistors, each of which has a gate electrode, a source electrode, and a drain electrode, the static RAM core cell comprising: two thin film transistors for switching, which are each connected to a bit line and a word line and select the recording and reading of data; and four thin film transistors for data storage, which are connected to a power supply voltage (Vdd) or a ground voltage (Vss) and allow the recording and reading of data, the static RAM core cell comprising: a first transistor layer comprising two thin film transistors selected from among the six thin film transistors; a second transistor layer which is positioned on the first transistor layer and comprises two thin film transistors selected from among the other four thin film transistors; and a third transistor layer which is positioned on the second transistor layer and comprises the other two thin film transistors, wherein the one or more kinds of electrodes of the first transistor layer and the one or more kinds of electrodes of the second transistor layer are electrically connected, and the one or more kinds of electrodes of the second transistor layer and the one or more kinds of electrodes of the third transistor layer are electrically connected. As such, the 3D static RAM core cell having a vertically stacked structure according to the present invention allows a complex patterning process for forming different types of organic transistors to be omitted during the manufacture of memory elements by disposing the same type of organic transistors on the same plane and vertically stacking same and can improve the degree of integration of a semiconductor circuit by reducing the area taken up by the memory elements.
展开▼