首页> 外国专利> 3D STATIC RAM CORE CELL HAVING VERTICALLY STACKED STRUCTURE, AND STATIC RAM CORE CELL ASSEMBLY COMPRISING SAME

3D STATIC RAM CORE CELL HAVING VERTICALLY STACKED STRUCTURE, AND STATIC RAM CORE CELL ASSEMBLY COMPRISING SAME

机译:具有垂直堆叠结构的3D静态RAM核心单元,以及包含相同组件的静态RAM核心单元

摘要

Disclosed is a 3D static RAM core cell having a vertically stacked structure, including six thin-film transistors each having a gate electrode, a source electrode and a drain electrode, the static RAM core cell including two switching thin-film transistors, each connected to a bit line and a word line to select recording and reading of data, and four data-storage thin-film transistors connected to a power supply voltage (Vdd) or a ground voltage (Vss) to record and read data, the static RAM core cell including a first transistor layer including two thin-film transistors selected from among the six thin-film transistors, a second transistor layer disposed on the first transistor layer and including two thin-film transistors selected from among the remaining four thin-film transistors, and a third transistor layer disposed on the second transistor layer and including the remaining two thin-film transistors, at least one electrode of the first transistor layer and at least one electrode of the second transistor layer being electrically connected to each other, and at least one electrode of the second transistor layer and at least one electrode of the third transistor layer being electrically connected to each other. Thereby, the static RAM core cell is configured such that organic transistors of the same type are arranged in the same plane and are vertically stacked, thus omitting a complicated patterning process for forming organic transistors of different types upon fabrication of a memory element, and also reducing the area occupied by the memory element to thereby increase the degree of integration of semiconductor circuits.
机译:公开了一种具有垂直堆叠结构的3D静态RAM核心单元,包括六个薄膜晶体管,每个薄膜晶体管具有栅极,源极和漏极,所述静态RAM核心单元包括两个开关薄膜晶体管,每个开关薄膜晶体管连接至一条位线和一条字线选择数据的记录和读取,以及四个连接到电源电压(Vdd)或接地电压(Vss)的数据存储薄膜晶体管,以记录和读取数据,静态RAM内核单元,包括第一晶体管层和第二晶体管层,第一晶体管层包括从六个薄膜晶体管中选择的两个薄膜晶体管;第二晶体管层设置在第一晶体管层上,第二晶体管层包括从其余四个薄膜晶体管中选择的两个薄膜晶体管;第三晶体管层,设置在第二晶体管层上,包括剩余的两个薄膜晶体管,第一晶体管层的至少一个电极和至少一个电极o在第二晶体管层彼此电连接的情况下,第二晶体管层的至少一个电极与第三晶体管层的至少一个电极彼此电连接。从而,静态RAM核心单元被配置为使得相同类型的有机晶体管被布置在相同的平面中并且被垂直地堆叠,从而省略了在制造存储元件时用于形成不同类型的有机晶体管的复杂的图案化工艺,并且减小存储元件所占据的面积,从而增加半导体电路的集成度。

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