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Long annealed integrated circuit arrangements and process for the production thereof

机译:长时间退火的集成电路装置及其生产方法

摘要

Integrated circuit arrangement (500, 500b),with an electrically conductive guide structure (506, 506b), which is structured in accordance with a grain structure,electrically conductive barrier material in a grain boundaries region of the guide structure (506, 506b) is arranged, the at least 5 nanometers or of the at least 10 nanometers is arranged in the interior of the guide structure,the circuit arrangement (500, 500b) contains a substrate (501), which contains a plurality of semiconductor components,the guide structure, and wherein a conductive path (506, 506b), wherein the conductive path (506, 506b) between the substrate (501) and a vialeitstruktur (550, 550b) adjacent to the vialeitstruktur (550, 550b) is arranged, wherein the vialeitstruktur (550, 550b) above the conductive path (506, 506b) is arranged,while a side wall of the vialeitstruktur (550, 550b) to a barrier material layer is adjacent and wherein between the vialeitstruktur and the conductive path (506, 506b) is no barrier material layer or not a continuous barrier material layer is arranged,and wherein the vialeitstruktur (550, 550b) to a remote from the conductive path (560, 560b), at the bottom surface of an electrically conductive barrier material layer (530, 530b) borders.
机译:具有根据晶粒结构构造的导电导引结构(506、506b)的集成电路装置(500、500b)是在导引结构(506、506b)的晶界区域中的导电阻挡材料布置在引导结构的内部中的至少5纳米或至少10纳米中,电路装置(500、500b)包含衬底(501),该衬底包含多个半导体组件,该引导结构,其中,导电路径(506、506b)布置在基板(501)和与通孔结构(550、550b)相邻的通孔结构(550、550b)之间的导电路径(506、506b),其中通孔结构(550、550b)布置在导电路径(506、506b)上方,而通孔结构(550、550b)的侧壁到阻挡材料层是相邻的,并且其中在通孔结构和导电路径(506、506b)之间不无聊布置材料层或不布置连续的阻挡层材料,并且其中,在导电阻挡层材料层(530、530b)的底表面处,通孔结构(550、550b)远离导电路径(560、560b)。 )边界。

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