Compact bicmos - voltage clamp for use in a cmos process

摘要

In the case of the proposed clamping structure for the derivation of esd - events, it is a combination of a lateral first mos - transistor (t1) and a second vertical bipolar transistor (t2). The construction has a second trough (pw) and the third tank (nw) of an opposite conductivity type, which come into contact with one another, that is to say have a common interface. The bulk of the first mos - transistor (t1) and the base of the vertical second bipolar transistor thus come into contact with each other, which results in an extremely compact design with good terminals performance allows.