ADAPTING NUMBER OF DATA POINTS PROCESSED IN PARALLEL TO MATCH SIZE OF DECOMPOSED FFTS

摘要

An embedded system (400) is described. The embedded system (400) includes a processing circuit (402) comprising a processing circuit (402) comprising 'Q' processing units that can be operated in parallel. The processing circuit (402) is configured to support an implementation of a non-power-of-2 fast Fourier transform (FFT) of length N using a multiplication of at least two smaller FFTs of a respective first length N1 and second length N2, where N1 and N2 are whole numbers. A memory (404) is operably coupled to the processing circuit (404) and includes at least input data. The processing circuit (402) is configured to: employ a customized instruction configured to perform an FFT operation of length less than 'Q' using a first of the at least two smaller FFTs, whereby the customized instruction writes results of the performed FFT on to memory (404) in multiples of less than 'Q' data points; and perform a FFT using the second of the at least two smaller FFTs.