ADAPTING NUMBER OF DATA POINTS PROCESSED IN PARALLEL TO MATCH SIZE OF DECOMPOSED FFTS

摘要

An embedded system (400) is described. The embedded system (400) includes a processing circuit (402) comprising at least one processor configured to support an implementation of a non-power-of-2 fast Fourier transform (FFT) of length N using a multiplication of at least two smaller FFTs of a respective first length N1 and second length N2, where N1 and N2 are whole numbers; and a memory (404), operably coupled to the processing circuit (404) and comprising at least input data. The processing circuit (402) is configured to: receive an input data complex number sequence; adapt the input data complex number sequence by inserting at least one zero into every X^th data point that results in an excess number (M) of data points above N, where X=N1, such that the inserted zeroes enables a use of a multiple-of-Q FFT; perform a first decomposed FFT of a respective first length N1 on the adapted input data complex number sequence and produce a first output complex number sequence; restore a number of data points of the first output complex number sequence to N after performing the first decomposed FFT; and perform a second decomposed FFT of a respective second length N2 on the first output complex number sequence that produces a second output complex number sequence.