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SEMI-DATA GATED FLOP WITH LOW CLOCK POWER/LOW INTERNAL POWER WITH MINIMAL AREA OVERHEAD
SEMI-DATA GATED FLOP WITH LOW CLOCK POWER/LOW INTERNAL POWER WITH MINIMAL AREA OVERHEAD
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机译:低时钟功率/低内部功率且具有最小面积开销的半数据门控触发器
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摘要
Methods and systems for clock gating are described herein. In certain aspects, a method for clock gating includes receiving an input signal of a flip-flop and an output signal of the flip-flop, and passing a clock signal to an input of a gate in the flip-flop if the input signal and the output signal have different logic values or both the input signal and the output signal have a logic value of zero. The method also includes gating the clock signal if both the input signal and the output signal have a logic value of one.
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