首页> 外国专利> Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP

Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP

机译:半导体器件和形成用于3-D FO-WLCSP的垂直互连结构的方法

摘要

A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the first insulating layer. An interconnect structure is formed through the encapsulant outside a footprint of the semiconductor die and electrically connected to the conductive layer. The first insulating layer includes an optically transparent or translucent material. The semiconductor die includes a sensor configured to receive an external stimulus passing through the first insulating layer. A second insulating layer is formed over the first surface of the semiconductor die. A conductive via is formed through the first insulating layer outside a footprint of the semiconductor die. A plurality of stacked semiconductor devices is electrically connected through the interconnect structure.
机译:半导体器件具有沉积在半导体管芯的第一表面上方和半导体管芯周围的密封剂。在半导体管芯的与第一表面相对的第二表面上方形成第一绝缘层。在第一绝缘层上方形成导电层。互连结构通过密封剂在半导体管芯的覆盖区外部形成并且电连接到导电层。第一绝缘层包括光学透明或半透明的材料。半导体管芯包括被配置为接收穿过第一绝缘层的外部刺激的传感器。在半导体管芯的第一表面上方形成第二绝缘层。在半导体管芯的覆盖区外部穿过第一绝缘层形成导电通孔。多个堆叠的半导体器件通过互连结构电连接。

著录项

  • 公开/公告号US2018026023A1

    专利类型

  • 公开/公告日2018-01-25

    原文格式PDF

  • 申请/专利权人 STATS CHIPPAC PTE. LTD.;

    申请/专利号US201715676488

  • 发明设计人 YAOJIAN LIN;KANG CHEN;SEUNG WOOK YOON;

    申请日2017-08-14

  • 分类号H01L25;H01L21/768;H01L23;H01L21/683;H01L23/522;H01L25/065;H01L23/552;H01L23/538;H01L23/498;H01L23/31;H01L21/56;H01L25/10;

  • 国家 US

  • 入库时间 2022-08-21 13:01:18

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号