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Inferring sampled data in decision feedback equalizer at restart of forwarded clock in memory system
Inferring sampled data in decision feedback equalizer at restart of forwarded clock in memory system
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机译:在内存系统中转发时钟重新启动时,在决策反馈均衡器中推断采样数据
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摘要
An apparatus includes a detector circuit and a data buffer. The detector circuit may be configured to (i) identify a start of a command sequence associated with a directed access to a memory system and (ii) generate a control signal indicating a non-consecutive clock associated with the start of the command sequence. The data buffer circuit may be configured to initialize a condition of a receiver circuit in response to the control signal prior to reception of a first data bit associated with the command sequence.
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