SEMICONDUCTOR DEVICE ELECTRONIC CONTROL SYSTEM AND METHOD FOR EVALUATING ELECTRONIC CONTROL SYSTEM

摘要

An objective of the present invention is to generate a false failure in a logic circuit without adding a new circuit to the logic circuit. A plurality of test points (TPs) each includes a test point flip-flop and fixes a target node within the logic circuit (LGC) at a prescribed logic level when the corresponding flip-flop holds a prescribed value. A scan chain (SC1) is configured by sequentially coupling a plurality of test point flip-flops. A failure injection circuit (ERINC1) injects a failure into the target node while the logic circuit (LGC) performs a normal operation by generating failure data (ERDT) and setting the generated failure data to the scan chain (SC1) through a scan-in node (SI1) of the scan chain (SC1).