ERROR CORRECTION CODE DECODER SHARING LOGIC OPERATION, MEMORY CONTROLLER INCLUDING SAME, AND ERROR CORRECTION CODE DECODING METHOD SHARING LOGIC OPERATION

摘要

An ECC decoder includes a finite state machine controller and a shared logic unit. The finite state machine controller generates a first control signal and a second control signal corresponding to each of a plurality of states. The shared logic unit includes a plurality of shared Galois field multipliers, shared XOR operators, and shared multiplexers, used for performing any one operation selected by the first control signal and the second control signal among a syndrome operation, an error location polynomial operation, an error location operation, and an error correction operation. Accordingly, the present invention can reduce the area of the ECC decoder.;COPYRIGHT KIPO 2018