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ERROR CORRECTION CODE (ECC) DECODERS SHARING LOGIC OPERATIONS, MEMORY CONTROLLERS INCLUDING THE ERROR CORRECTION CODE DECODERS, AND METHODS OF DECODING ERROR CORRECTION CODES
ERROR CORRECTION CODE (ECC) DECODERS SHARING LOGIC OPERATIONS, MEMORY CONTROLLERS INCLUDING THE ERROR CORRECTION CODE DECODERS, AND METHODS OF DECODING ERROR CORRECTION CODES
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机译:共享逻辑操作的纠错码(ECC)解码器,包含纠错码解码器的内存控制器以及解码纠错码的方法
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摘要
An error correction code (ECC) decoder includes a finite state machine (FSM) controller and a shared logic circuit. The FSM controller generates a first control signal and a second control signal each corresponding to a certain state. The shared logic circuit includes a plurality of shared Galois field (GF) multipliers, a plurality of shared XOR arithmetic elements, and a plurality of shared multiplexers (MUXs), which are used for an operation selected between a syndrome operation, an error location polynomial operation, an error location operation and an error correction operation, in response to the first and second control signals.
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