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Two Bit Overlap: A Class of Double Error Correction One Step Majority Logic Decodable Codes

机译:两位重叠:一类双误差校正一步大多数逻辑可解码码

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Error Correction Codes (ECCs) are commonly used to protect memories against soft errors with an impact on memory area and delay. For large memories, the area overhead is mostly due to the additional cells needed to store the parity check bits. In terms of delay, the overhead is mostly needed to detect and correct errors when the data is read from the memory. Most ECCs that can correct more than one error have a complex decoding process and so are limited in high speed memory applications. One exception is One Step Majority Logic Decodable (OS-MLD) codes for which decoding can be done in parallel at high speed. Unfortunately, there are only a few OS-MLD codes that provide a limited choice in terms of block sizes, error correction capabilities and code rate. Therefore, there is considerable interest in a novel construction of OS-MLD codes to provide additional choices for protecting memories. In this paper, a new method to construct Double Error Correction (DEC) OS-MLD codes is presented. This method is based on the use of parity check matrices in which two bits have at most two parity check equations in common; the proposed method provides codes that require a smaller number of parity check bits than existing codes like Orthogonal Latin Square (OLS) codes. The drawback of the proposed Two Bit Overlap (TBO) codes is that they require slightly more complex decoding than OLS codes. Therefore, they provide an intermediate solution between OLS and non OS-MLD codes in terms of decoding delay and number of parity check bits. The proposed TBO codes have been implemented for some block sizes and compared to both OLS and BCH codes to illustrate the trade off in delay and memory overhead. Finally, this paper discusses the generalization of the proposed scheme to codes with larger error correction capabilities.
机译:误差校正码(ECC)通常用于保护对软误差的存储器,对存储区域和延迟产生影响。对于大存储器,区域开销主要是由于存储奇偶校验位所需的附加单元。在延迟方面,当从存储器读取数据时,大多数需要检测和更正错误。大多数可以纠正多个错误的ECC具有复杂的解码过程,并且在高速存储器应用中受到限制。一个例外是一个阶梯多数逻辑可解码(OS-MLD)代码,用于以高速进行解码的解码。不幸的是,只有几个OS-MLD代码在块大小,纠错功能和代码率方面提供有限的选择。因此,对OS-MLD码的新建建设具有相当大的兴趣,以提供保护存储器的额外选择。在本文中,提出了一种构建双误差校正(DEC)OS-MLD代码的新方法。该方法基于使用奇偶校验矩阵,其中两位具有最多两个奇偶校验方程式的奇偶校验方程;该方法提供了比正交拉丁广场(OLS)代码等现有代码需要较少数量的奇偶校验校验位的代码。提出的两位重叠(TBO)代码的缺点是它们需要比OLS代码更复杂的解码。因此,它们在解码延迟和奇偶校验位数方面提供OLS和非OS-MLD代码之间的中间解决方案。所提出的TBO码已经为某些块大小实施,并与OLS和BCH码相比,以说明延迟和内存开销的折衷。最后,本文讨论了提出的方案的概括,以较大的纠错能力较大。

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