DUAL-SPLIT MONOTONIC SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER

摘要

The present invention relates to a dual-split monotonic successive approximation register analog to digital converter which comprises: a sample hold unit receiving a first input signal (V_ip) and a second input signal (V_in) as input signals in response to switching control by a successive approximation register (SAR) control logic to perform sample operation and hold operation; a capacitor array generating a first output signal and a second output signal as output voltage values, respectively in response to the first input signal and the second input signal during the period of the sample hold, wherein the capacitor array is formed in a two-tier structure for determining a high-order bit or a low-order bit by using two bridge capacitors (C_B1, C_B2); switches (S7, LSB_SW) interworking with the sample hold unit to determine the high-order bit or the low-order bit; a comparison unit comparing the size of the first output signal with that of the second output signal to output a digital value according to the result of the comparison; and a successive approximation register control logic outputting the final digital code value as a result signal in response to the digital value. According to the present invention, a combination of a dual-split form and a monotonic form is expected to have effects such as the decreased number of capacitors, enhanced energy efficiency, a realizable size of a capacitor, enhanced accuracy and the like.;COPYRIGHT KIPO 2018