A wafer-level packaging process using wafer through holes with low aspect ratio sidewalls

摘要

A method for manufacturing wafer-level packages for integrated circuits, the method comprising: providing an IC base wafer comprising a plurality of chips and at least one contact point electrically connected to a chip on a surface of the IC base wafer, respectively; Providing a lid wafer comprising a polished semiconductor substrate having a front surface and a back surface; Providing a plurality of pits having low aspect ratio sidewalls on the front surface of the semiconductor substrate; Providing a recess having low aspect ratio sidewalls on the back surface of the semiconductor substrate, wherein each of the recesses on the front surface and the recess on the back surface of the semiconductor substrate has four trapezoidal sidewalls and a planar lower portion, providing dimples with low aspect ratio sidewalls; Provide sidewall slopes that are no steeper than 1 vertical: 1 horizontal; Removing portions of the lower portion of the recess on the back surface of the semiconductor substrate to provide a connection via between adjacent recesses on the front surface; Depositing an electrically conductive metal or solder on surfaces of the sidewalls and the interconnecting contact hole to provide a wafer through sidewall electrical connection; and attaching the cap wafer to the IC base wafer to form a composite wafer so that the at least one electrical contact point disposed on the surface of the IC base wafer is electrically connected to the electrical wafer via sidewall connection and each chip is inserted through a corresponding recess on the wafer Front surface of the semiconductor substrate provided environment is arranged.