A memory lock (100) comprising: a first TFET (102); a capacitor (104); a storage node (108) formed by connecting a first terminal (106) of the capacitor (104) to a first electrode of the first TFET; a control circuit capable of supplying a first electrical potential on a second capacitor terminal (110), a second electrical potential on the gate of the first TFET and a third electrical potential on a second electrode of the first TFET, so that: when the bit stored is low, the first TFET is reverse-biased with a conduction current obtained by band-band tunneling, with a value greater than a capacitor leakage current; • when the stored bit is high, the first TFET is reverse biased with a blocking current value lower than the capacitor leakage current.
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