An apparatus (2) has first processing circuitry (6) and second processing circuitry (4). The second processing circuitry 4 has at least one hardware mechanism (10), (30) providing a greater level of fault protection or fault detection than is provided for the first processing circuitry (6). Coherency control circuitry (45, 80, 82) controls access to data from at least part of a shared address space by the first and second processing circuitry (6, 4) according to an asymmetric coherency protocol in which a local-only update of data in a local cache (8) of the first processing circuitry (6) is restricted in comparison to a local-only update of data in a local cache (8) of the second processing circuitry (4).
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