Avoiding deadlocks in processor-based systems that use retry bus coherency protocols and in-order response non-retry bus coherency protocols

摘要

Aspects disclosed herein include avoiding deadlocks in processor-based systems that use retry bus coherency protocols and in-order response non-retry bus coherency protocols. In this regard, the interface bridge circuit is communicatively coupled to a first core device that implements a retry bus coherency protocol and a second core device that implements an in-order response non-retry bus coherency protocol. The interface bridge circuit receives the snoop command from the first core device and transfers the snoop command to the second core device. While the snoop command is pending, the interface bridge circuit detects a potential deadlock condition between the first core device and the second core device. The interface bridge circuit is configured to send a retry response to the first core device in response to detecting a potential deadlock condition. This allows the first core device to continue processing, thereby eliminating potential deadlock conditions.