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Product-sum operation unit, logic operation device, neuromorphic device and product-sum operation method

机译:积和运算单元,逻辑运算装置,神经形态装置和积和运算方法

摘要

The product-sum operation unit corresponds to an input value, multiplies an input signal having a rising portion, a signal portion, and a falling portion by a weight to generate an output signal, and outputs the output signal, and a plurality of product operation portions A sum operation unit that calculates the sum of the output signals output from each of the plurality of product operation units; and the sum due to a current flowing into variable resistors of the plurality of product operation units due to the rising portion of the input signal A correction value including at least one of a second value to be incorporated into the sum by the current flowing into the variable resistors of the plurality of product operation units due to the first value incorporated into the first signal and the falling portion of the input signal And a correction unit that executes a correction process that corrects the total sum of the output signals on the basis of the above.
机译:乘积和运算单元对应于输入值,将具有上升部分,信号部分和下降部分的输入信号乘以权重以生成输出信号,并输出该输出信号,并进行多次积运算部分求和运算单元,其计算从多个乘积运算单元中的每一个输出的输出信号的总和;由于输入信号A的上升部分,电流流入多个乘积运算单元的可变电阻器中的总和包括校正值,该校正值包括第二值中的至少一个,该第二值将通过流入该运算器的电流而被合并到总和中。由于结合到第一信号中的第一值和输入信号的下降部分,多个乘积运算单元的可变电阻器;以及校正单元,其执行校正过程,该校正过程基于输出信号的总和来校正输出信号的总和。以上。

著录项

  • 公开/公告号JP6540931B1

    专利类型

  • 公开/公告日2019-07-10

    原文格式PDF

  • 申请/专利权人 TDK株式会社;

    申请/专利号JP20190512843

  • 发明设计人 伊藤 邦恭;柴田 竜雄;

    申请日2018-10-11

  • 分类号G06G7/60;

  • 国家 JP

  • 入库时间 2022-08-21 12:19:32

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