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Delay propagation for multiple logic cells using correlation and coskewness of delays and slew rates in an integrated circuit design
Delay propagation for multiple logic cells using correlation and coskewness of delays and slew rates in an integrated circuit design
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机译:在集成电路设计中使用延迟和转换率的相关性和偏度,对多个逻辑单元进行延迟传播
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摘要
A method as provided includes retrieving a correlation value from a correlation table and a coskewness value from a coskewness table. The correlation value includes a correlation between a delay distribution and a slew rate distribution, and is associated with both: an input slew rate and an output load, in a logic stage in an integrated circuit design, and the coskewness value is a coskewness between the delay distribution and the slew rate distribution. The method includes determining a partial derivative of a delay function relative to the input slew rate, determining a delay distribution for a signal through a plurality of logic stages using the correlation value, the coskewness value, and the partial derivative of the delay function relative to the input slew rate. The method also includes verifying that a statistical value of the delay distribution satisfies a desired performance value for an integrated circuit.
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