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Delay propagation for multiple logic cells using correlation and coskewness of delays and slew rates in an integrated circuit design

机译:在集成电路设计中使用延迟和转换率的相关性和偏度,对多个逻辑单元进行延迟传播

摘要

A method as provided includes retrieving a correlation value from a correlation table and a coskewness value from a coskewness table. The correlation value includes a correlation between a delay distribution and a slew rate distribution, and is associated with both: an input slew rate and an output load, in a logic stage in an integrated circuit design, and the coskewness value is a coskewness between the delay distribution and the slew rate distribution. The method includes determining a partial derivative of a delay function relative to the input slew rate, determining a delay distribution for a signal through a plurality of logic stages using the correlation value, the coskewness value, and the partial derivative of the delay function relative to the input slew rate. The method also includes verifying that a statistical value of the delay distribution satisfies a desired performance value for an integrated circuit.
机译:所提供的方法包括从相关性表中检索相关性值和从偏度表中检索偏度值。该相关值包括延迟分布和转换速率分布之间的相关性,并且在集成电路设计的逻辑阶段中与输入转换速率和输出负载这两者相关联,并且偏度值是该斜率值与斜率之间的偏度。延迟分布和摆率分布。该方法包括:确定相对于输入转换速率的延迟函数的偏导数;使用相关值,偏度值和相对于输入函数的偏函数的偏导数,确定通过多个逻辑级的信号的延迟分布。输入摆率。该方法还包括验证延迟分布的统计值满足集成电路的期望性能值。

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