首页> 外国专利> METHOD OF PROVIDING SOURCE AND DRAIN DOPING FOR CMOS ARCHITECTURE INCLUDING FINFET AND SEMICONDUCTOR DEVICES SO FORMED

METHOD OF PROVIDING SOURCE AND DRAIN DOPING FOR CMOS ARCHITECTURE INCLUDING FINFET AND SEMICONDUCTOR DEVICES SO FORMED

机译:包括finFET和半导体器件的CMOS结构提供源极和漏极掺杂的方法

摘要

A method for providing a semiconductor device and the device so formed are described. A doped semiconductor layer is deposited on a semiconductor underlayer. At least a portion of the semiconductor underlayer is exposed. A dopant for the doped semiconductor layer is selected from a p-type dopant and an n-type dopant. An ultraviolet-assisted low temperature (UVLT) anneal of the doped semiconductor layer is performed in an ambient. The ambient is selected from an oxidizing ambient and a nitriding ambient. The oxidizing ambient is used for the n-type dopant. The nitriding ambient is used for the p-type dopant. A sacrificial layer is formed by the doped semiconductor layer during the UVLT anneal. The dopant is driven into the portion of the semiconductor underlayer from the doped semiconductor layer by the UVLT anneal, thereby forming a doped semiconductor underlayer. The sacrificial layer is then removed.
机译:描述了一种用于提供半导体器件的方法和如此形成的器件。掺杂的半导体层沉积在半导体底层上。半导体底层的至少一部分被暴露。用于掺杂半导体层的掺杂剂选自p型掺杂剂和n型掺杂剂。在环境中对掺杂的半导体层进行紫外线辅助的低温(UVLT)退火。该环境选自氧化环境和氮化环境。氧化环境用于n型掺杂剂。氮化环境用于p型掺杂剂。在UVLT退火期间,由掺杂的半导体层形成牺牲层。通过UVLT退火将掺杂剂从掺杂的半导体层驱动到半导体底层的该部分中,从而形成掺杂的半导体底层。然后去除牺牲层。

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