首页> 外国专利> METHOD AND SYSTEM FOR COMPENSATING FOR FLOATING GATE-TO-FLOATING GATE (FG-FG) INTERFERENCE IN FLASH MEMORY CELL READ OPERATIONS

METHOD AND SYSTEM FOR COMPENSATING FOR FLOATING GATE-TO-FLOATING GATE (FG-FG) INTERFERENCE IN FLASH MEMORY CELL READ OPERATIONS

机译:补偿闪存存储单元读取操作中的浮动门到浮动门(FG-FG)干扰的方法和系统

摘要

Embodiments of the present disclosure provide methods, devices, modules, and systems for compensating for floating gate to floating gate (fg-fg) interference in flash memory cell read operations. Compensating for fg-fg interference effects can reduce or prevent read errors. Embodiments of the present disclosure can compensate for fg-fg interference by determining the programmed state of aggressor (or influencing) memory cells that are programmed after a target memory cell. If the aggressor memory cell is in the erased state of Level 0 or is in a programmed state of Level 2-15, the target memory cell is identified as undisturbed. If the aggressor memory cell is programmed to a Level 1 (instead of Level 0 or Levels 2-15), the target memory cell is identified as disturbed. If the target memory cell is disturbed, sensing parameters may be adjusted to compensate for the disruption.
机译:本公开的实施例提供了用于补偿闪存单元读取操作中的浮栅到浮栅(fg-fg)干扰的方法,设备,模块和系统。补偿fg-fg干扰影响可以减少或防止读取错误。本公开的实施例可以通过确定在目标存储单元之后被编程的侵害者(或影响)存储单元的编程状态来补偿fg-fg干扰。如果攻击者存储单元处于级别0的已擦除状态或处于级别2-15的编程状态,则目标存储单元被标识为未受干扰。如果将攻击者存储单元编程为1级(而不是0级或2-15级),则将目标存储单元标识为受干扰。如果目标存储单元受到干扰,则可以调整感测参数以补偿破坏。

著录项

  • 公开/公告号US2019043565A1

    专利类型

  • 公开/公告日2019-02-07

    原文格式PDF

  • 申请/专利权人 INTEL CORPORATION;

    申请/专利号US201715848948

  • 发明设计人 CARMINE MICCOLI;AKIRA GODA;

    申请日2017-12-20

  • 分类号G11C11/56;G11C16/34;G11C16/04;G11C29/50;

  • 国家 US

  • 入库时间 2022-08-21 12:04:06

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