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minimum footprint standard cell circuits for reduced area

机译:最小占位面积的标准单元电路,可减小面积

摘要

standard minimum-lane, reduced-area cell circuits are provided. in one aspect, a minimum track pattern cell circuit employs a first high aspect ratio voltage rail disposed over a first half track and configured to provide a first voltage (e.g., vdd) to the track pattern cell circuit minimum. a second high aspect ratio tension rail is disposed on a second half track substantially parallel to the first high aspect ratio tension rail. The second high aspect ratio voltage rail is configured to provide a second voltage lower than the first voltage (e.g., vss) for the minimum track standard cell circuit. The standard minimum track cell circuit employs multiple tracks arranged between the first and second half tracks. The number of trails may be limited based on particular factors. Track minimization reduces area compared to standard standard cell circuits.
机译:提供标准的最小车道,面积缩小的单元电路。在一个方面,最小轨道图案单元电路采用第一高纵横比电压轨,该电压高电压轨布置在第一半轨道上并且配置为向轨道图案单元电路最小值提供第一电压(例如,vdd)。第二高纵横比张力轨设置在基本平行于第一高纵横比张力轨的第二半轨道上。第二高纵横比电压轨被配置为为最小轨道标准单元电路提供低于第一电压的第二电压(例如,vss)。标准最小轨道单元电路采用布置在第一和第二半轨道之间的多个轨道。路径的数量可能会基于特定因素而受到限制。与标准的标准单元电路相比,走线最小化减少了面积。

著录项

  • 公开/公告号BR112019004570A2

    专利类型

  • 公开/公告日2019-06-11

    原文格式PDF

  • 申请/专利权人 QUALCOMM INCORPORATED;

    申请/专利号BR20191104570

  • 申请日2017-09-14

  • 分类号H01L27/02;H01L27/118;

  • 国家 BR

  • 入库时间 2022-08-21 12:03:22

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