CELL ARCHITECTURE WITH INTRINSIC DECOUPLING CAPACITOR

摘要

An IC includes an array of cells and a first set of endcap cells. The array of cells includes a first set of M_x layer power interconnects coupled to a first voltage, a first set of M_x layer interconnects, a second set of M_x layer power interconnects coupled to a second voltage source, and a second set of M_x layer interconnects. The first set of endcap cells includes first and second sets of M_x+1 layer interconnects. The first set of M_x+1 layer interconnects is coupled to the first set of M_x layer power interconnects and to the second set of Mx layer interconnects to provide a first set of decoupling capacitors. The second set of M_x+1 layer interconnects is coupled to the second set of Mx layer power interconnects and to the first set of M_x layer interconnects to provide a second set of decoupling capacitors.