THREE-DIMENSIONAL INTEGRATED CIRCUIT MEMORY CELL HAVING A FERROELECTRIC FIELD EFFECT TRANSISTOR WITH A FLOATING GATE

摘要

A three-dimensional integrated circuit memory device may be fabricated to have memory cells comprising a layered stack structure formed from a plurality of dielectric layers and at least one conductive layer positioned between adjacent dielectric layers of the plurality of dielectric layers. A via may be defined by a sidewall extending through the layered stack structure and a gate dielectric layer may be formed within the via. A channel material layer may be formed within the via contacting the gate dielectric layer. A floating gate material layer may be formed between adjacent dielectric layers of the plurality of dielectric layers, wherein the floating gate material layer contacts the channel material layer. A ferroelectric material layer may be formed between adjacent dielectric layers of the plurality of dielectric layers, wherein the ferroelectric material layer contacts the floating gate material layer and the at least one conductive layer.