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3 method of testing 3D type multi layer semiconductor device in the process of stacking chip

机译:3在堆叠过程中测试3D型多层半导体器件的方法

摘要

Disclosed is an intermediate inspection method for a chip stacking process of a 3D multilayer semiconductor device. According to the present invention, the intermediate inspection method performs optical inspection with pattern inspection equipment having an auto-focusing function while relatively moving on a plane between an optical inspection system and an object when an upper chip is stacked after a stacking step of stacking the upper chip on a lower chip in a 3D multilayer semiconductor device manufacturing process to detect a position change in the height direction on a surface of the upper chip, and determines chip stacking defect at the position of the corresponding upper chip based on a detection result. Accordingly, a defective chip portion, which may cause a vertical contact defect, is checked through an optical inspection for a portion exposed to the outside while stacking up a chip in a process for forming a 3D multilayer semiconductor device such that following processes are prevented from being performed in the portion, thereby reducing processing load and cost and a defective rate of the completed 3D multilayer semiconductor device.
机译:公开了一种用于3D多层半导体器件的芯片堆叠工艺的中间检查方法。根据本发明,当在堆叠上芯片的堆叠步骤之后堆叠上芯片时,中间检查方法利用具有自动聚焦功能的图案检查设备执行光学检查,同时在光学检查系统和物体之间的平面上相对移动。在3D多层半导体器件制造过程中,在下部芯片上的上部芯片进行检测,以检测上部芯片的表面在高度方向上的位置变化,并基于检测结果确定在相应的上部芯片的位置处的芯片堆叠缺陷。因此,在形成3D多层半导体器件的过程中,在堆叠芯片的同时,通过光学检查来检查可能引起垂直接触缺陷的有缺陷的芯片部分,以检查暴露于外部的部分,从而防止后续的过程通过在该部分中进行制造,从而降低了加工负荷和成本,并降低了完成的3D多层半导体器件的不良率。

著录项

  • 公开/公告号KR20190082508A

    专利类型

  • 公开/公告日2019-07-10

    原文格式PDF

  • 申请/专利权人 NEXTIN INC.;

    申请/专利号KR20180000188

  • 发明设计人 PARK TAE HOON;JEONG JUN HEE;

    申请日2018-01-02

  • 分类号H01L21/66;

  • 国家 KR

  • 入库时间 2022-08-21 11:50:24

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