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3 method of testing 3D type multi layer semiconductor device in the process of stacking chip

机译:3在堆叠过程中测试3D型多层半导体器件的方法

摘要

After the stacking process step of performing the upper chip stacking process on the lower chip in the process of manufacturing the three-dimensional stacked semiconductor device, a pattern inspection device having an auto-focus function with the upper chip stacked, Detecting a change in height position of the upper chip surface by performing optical inspection while relatively moving the position on the upper chip position and determining a chip stacking failure at the upper chip position based on the detected result, An interim inspection method for a semiconductor device chip stacking process is disclosed. According to the method of the present invention, in the step of forming a three-dimensional laminated semiconductor device, a portion of a defective chip, which may cause a defective vertical connection, is identified through optical inspection of a portion exposed to the outside while stacking chips, It is possible to reduce the process burden and the cost, and to reduce the defective ratio of the completed three-dimensional stacked semiconductor device.
机译:在制造三维堆叠式半导体器件的过程中,在下芯片上执行上芯片堆叠工艺的堆叠工艺步骤之后,具有自动聚焦功能的图案检查设备将上芯片堆叠在一起,从而检测高度变化通过在相对移动上芯片位置上的位置并基于检测结果确定上芯片位置处的芯片堆叠失败的同时执行光学检查来进行上芯片表面的位置检测,公开了一种用于半导体器件芯片堆叠过程的临时检查方法。根据本发明的方法,在形成三维层压半导体器件的步骤中,通过光学检查暴露于外部的部分来识别可能引起垂直连接不良的缺陷芯片的一部分。堆叠芯片,可以减少工艺负担和成本,并且可以降低完成的三维堆叠半导体器件的不良率。

著录项

  • 公开/公告号KR101999210B1

    专利类型

  • 公开/公告日2019-07-11

    原文格式PDF

  • 申请/专利权人 (주)넥스틴;

    申请/专利号KR20180000188

  • 发明设计人 박태훈;정준희;

    申请日2018-01-02

  • 分类号H01L21/66;

  • 国家 KR

  • 入库时间 2022-08-21 11:48:12

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