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Techniques for mitigating high-latency instructions in high-traffic execution paths

机译:缓解高流量执行路径中高延迟指令的技术

摘要

Embodiments may be directed to techniques for executing a binary code based on source code comprising basic instruction blocks, identifying an execution path of a plurality of basic instruction blocks having a higher execution frequency than an execution frequency threshold, and last branch data records for the plurality of bases Capture instruction blocks, wherein the records of the last branch should indicate the execution times for the plurality of basic instruction blocks. Further, embodiments include determining latency values for each of the plurality of basic instruction blocks based on the execution times and performing an attenuation operation for each of the plurality of basic instruction blocks whose latency values are above a latency threshold.
机译:实施例可以针对用于基于包括基本指令块的源代码执行二进制代码,识别具有比执行频率阈值更高的执行频率的多个基本指令块的执行路径,以及用于多个的最后分支数据记录的技术。基数捕获指令块,其中最后分支的记录应指示多个基本指令块的执行时间。此外,实施例包括基于执行时间来确定多个基本指令块中的每个基本指令块的等待时间值,以及对延迟时间值高于等待时间阈值的多个基本指令块中的每个基本指令块执行衰减操作。

著录项

  • 公开/公告号DE102018127141A1

    专利类型

  • 公开/公告日2019-05-29

    原文格式PDF

  • 申请/专利权人 INTEL CORPORATION;

    申请/专利号DE201810127141

  • 发明设计人 KSHITIJ DOSHI;HARSHAD SANE;

    申请日2018-10-30

  • 分类号G06F9/28;

  • 国家 DE

  • 入库时间 2022-08-21 11:44:40

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