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Compile-time decided instruction cache locking using worst-case execution paths

机译：编译时决定使用最坏情况执行路径的指令高速缓存锁定

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Heiko Falk; Sascha Plazar; Henrik Theiling;
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年度 2007
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1. Analyzing the Worst-Case Execution Time for Instruction Caches with Prefetching [J] . JUN YAN, WEI ZHANG ACM Transactions on Embedded Computing Systems . 2009,第1期

机译：通过预取分析指令高速缓存的最坏情况执行时间
2. Cache-Aware SPM Allocation to Reduce Worst-Case Execution Time for Hybrid SPM-Caches [J] . Wu Lan, Zhang Wei Journal of circuits, systems and computers . 2018,第5期

机译：缓存感知SPM分配可减少混合SPM缓存的最坏情况执行时间
3. Combining Symbolic Execution and Path Enumeration in Worst-Case Execution Time Analysis [J] . Djemai Kebbal, Pascal Sainrat OASIcs : OpenAccess Series in Informatics . 2006,第1期

机译：在最坏情况下执行时间分析中结合符号执行和路径枚举
4. Compile-time decided instruction cache locking using worst-case execution paths [C] . Heiko Falk, Sascha Plazar, Henrik Theiling, IEEE/ACM international conference on Hardware/software codesign and system synthesis . 2007

机译：使用最坏情况的执行路径锁定编译时决定的指令高速缓存
5. Worst-case performance analysis of low-power instruction caches. [D] . Al-Tarawneh, Mutaz. 2008

机译：低功耗指令缓存的最坏情况性能分析。
6. Reducing the WCET and analysis time of systems with simple lockable instruction caches [O] . Alba Pedro-Zapater, Juan Segarra, Rubén Gran Tejero, 2020

机译：用简单的可锁定指令缓存减少WCET和分析时间
7. Combining Symbolic Execution and Path Enumeration in Worst-Case Execution Time Analysis [O] . Kebbal Djemai, Sainrat Pascal, Compilers and WCET 2006

机译：在最坏情况执行时间分析中结合符号执行和路径枚举

Compile-time decided instruction cache locking using worst-case execution paths

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