INTEGRATION OF MEMORY TRANSISTOR INTO HIGH-K, METAL GATE CMOS PROCESS FLOW

摘要

To provide memory cells including embedded SONOS based non-volatile memory (NVM) transistors and MOS transistors and methods for fabricating the same.SOLUTION: A method for fabricating memory cells includes the steps of: forming a gate stack 228 of a NVM transistor 206 in a NVM region 208 of a substrate 204 that includes the NVM region and a plurality of MOS regions 212a-212c; and depositing a high-k dielectric material over the gate stack of the NVM transistor and the MOS regions so as to form concurrently the high-k dielectric material on the gate stack of the NVM transistor and a blocking dielectric including a high-k gate dielectric on the MOS regions. A first metal layer is deposited over the high-k dielectric material to be patterned so that a metal gate over the gate stack of the NVM transistor and a metal gate for a field effect transistor in one MOS region are formed concurrently.SELECTED DRAWING: Figure 2-2