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SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR, POWER CONVERSION DEVICE, THREE-PHASE MOTOR SYSTEM, VEHICLE, AND RAILWAY VEHICLE

机译:半导体装置及其制造方法,功率转换装置,三相电动机系统,车辆和铁路车辆

摘要

To provide a power semiconductor device having high performance and high reliability.SOLUTION: A semiconductor device includes: a first conductivity type semiconductor substrate; a drain electrode formed on the rear surface side of the semiconductor substrate; a first conductivity type drift layer formed on the semiconductor substrate; a second conductivity type body layer; a first conductivity type JFET region interposed between body layers; a first conductivity type source region that is connected to a source electrode and is formed in the body layer; a first conductivity type first current diffusion layer that is connected to the source region and has a concentration lower than that of the source region; a second conductivity type first electric field relaxation layer formed on the first current diffusion layer; a first conductivity type second current diffusion layer that is connected to the JFET region and has a concentration equal to that of the first current diffusion layer; a second conductivity type second electric field relaxation layer formed on the second current diffusion layer; a trench that extends to the first current diffusion layer, the first electric field relaxation layer, the body layer, the second current diffusion layer, and the second electric field relaxation layer, is located at a position shallower than that of the body layer, and has a bottom surface in contact with the body layer; a gate insulation film formed on an inner wall of the trench; and a gate electrode formed on the gate insulation film.SELECTED DRAWING: Figure 2
机译:为了提供一种具有高性能和高可靠性的功率半导体器件。漏电极形成在半导体基板的背面侧。在半导体衬底上形成的第一导电类型漂移层;第二导电型体层;插入在主体层之间的第一导电类型的JFET区域;在主体层中形成有与源电极连接的第一导电型源区域。第一导电类型的第一电流扩散层,其连接到源极区域并且具有低于源极区域的浓度的浓度;在第一电流扩散层上形成的第二导电类型的第一电场缓和层;第一导电型第二电流扩散层,其连接至所述JFET区域,并且具有与所述第一电流扩散层相同的浓度;在第二电流扩散层上形成的第二导电型第二电场缓和层;延伸到第一电流扩散层,第一电场缓和层,主体层,第二电流扩散层和第二电场缓和层的沟槽位于比主体层浅的位置,并且具有与主体层接触的底表面;在沟槽的内壁上形成的栅绝缘膜;并在栅绝缘膜上形成栅电极。选图:图2

著录项

  • 公开/公告号JP2019207906A

    专利类型

  • 公开/公告日2019-12-05

    原文格式PDF

  • 申请/专利权人 HITACHI LTD;

    申请/专利号JP20180101322

  • 发明设计人 TEGA NAOKI;SUTO TAKERU;WATANABE NAOKI;

    申请日2018-05-28

  • 分类号H01L29/78;H01L29/12;H01L29/06;H01L21/336;H01L21/28;

  • 国家 JP

  • 入库时间 2022-08-21 11:31:44

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