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Memory device accessed in consideration of data locality and electronic system including the same

机译:考虑到数据局部性而访问的存储设备以及包括该存储设备的电子系统

摘要

A memory device includes a memory cell array, a row decoder, a multi-column decoder, a gating circuit, and an input/output data driving circuit. The memory cell array includes a plurality of memory cells arranged to form a plurality of rows and a plurality of columns. The row decoder generates a row selection signal based on a row address to select a target row from the rows. The multi-column decoder generates a multi-column selection signal based on a column address and column selection information to select a plurality of target columns from columns included in the target row at a time. The gating circuit selects the target columns at a time based on the multi-column selection signal. The input/output data driving circuit writes input data to the target columns at a time or outputs data stored in the target columns at a time as output data through the gating circuit based on the multi-column selection signal and a data mask signal. Column addresses corresponding to the target columns included in the target row are not consecutive.
机译:存储装置包括存储单元阵列,行解码器,多列解码器,门控电路和输入/输出数据驱动电路。存储单元阵列包括布置成形成多行和多列的多个存储单元。行解码器基于行地址生成行选择信号,以从行中选择目标行。多列解码器基于列地址和列选择信息生成多列选择信号,以一次从目标行中包括的列中选择多个目标列。门控电路基于多列选择信号一次选择目标列。输入/输出数据驱动电路基于多列选择信号和数据屏蔽信号,一次通过门控电路将输入数据一次写入目标列或一次输出存储在目标列中的数据作为输出数据。与目标行中包括的目标列相对应的列地址不连续。

著录项

  • 公开/公告号US10691608B2

    专利类型

  • 公开/公告日2020-06-23

    原文格式PDF

  • 申请/专利权人 JAESOP KONG;

    申请/专利号US201715851775

  • 发明设计人 JAESOP KONG;

    申请日2017-12-22

  • 分类号G06F12/08;G06F12/0882;G06F3/06;G11C8/10;G11C8/12;G11C7/12;G11C7/10;G06F13/16;G06F12/1045;G06F12/02;

  • 国家 US

  • 入库时间 2022-08-21 11:31:09

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