首页>
外国专利>
ULTRA LOW PARASITIC INDUCTANCE INTEGRATED CASCODE GaN DEVICES
ULTRA LOW PARASITIC INDUCTANCE INTEGRATED CASCODE GaN DEVICES
展开▼
机译:超低寄生电感集成CASCODE GaN器件
展开▼
页面导航
摘要
著录项
相似文献
摘要
One silicon MOSFET transistor, which is used as the VThreshold control, and a GaN power HEMT are integrated on a single die to enable a fully integrated depletion-mode power device. GaN area is created on a silicon substrate and GaN FETs are built in the GaN area. Outside of the GaN area, silicon transistors such as switch MOSFETs are built. Front end of line or back end of line metal connections are then made to create interconnections among the GaN FET and the silicon transistor. The short physical proximity of the silicon transistor and GaN HEMT significantly reduces the parasitic resistance and inductance between them. Thus, high speed signals are able to travel from the silicon transistor to the GaN HEMT with a higher frequency and lower distortion, without creating overshoot voltage when there is large parasitic inductance. Therefore, the cascode device can operate at a higher switching frequency.
展开▼