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System and Method for Receiver Equalization and Stressed Eye Testing Methodology for DDR5 Memory Controller

机译:DDR5存储器控制器的接收机均衡和应力眼测试方法的系统和方法

摘要

A method for bit error rate testing a processing unit using a bit error rate tester (BERT) includes transmitting a signal pair to a receiver of the processing unit, the signal pair having jitter levels complying with a jitter threshold, tuning the signal pair to obtain a first stressed eye measurement for the receiver, wherein the first stressed eye measurement complies with a stressed eye mask, placing the processing unit into a loop-back mode, wherein data transmitted to the processing unit by the BERT is transmitted back to the BERT, transmitting a data pattern to the processing unit, receiving a looped back version of the data pattern from the processing unit, and calculating a bit error rate in accordance with the data pattern and the looped back version of the data pattern.
机译:一种用于使用误码率测试器(BERT)测试处理单元的误码率的方法,包括将信号对发送到处理单元的接收器,该信号对具有符合抖动阈值的抖动水平,调整该信号对以获得用于接收器的第一压力眼图测量,其中,第一压力眼图与压力眼罩相符,将处理单元置于环回模式,其中,由BERT发送到处理单元的数据被发送回BERT,向处理单元发送数据模式,从处理单元接收数据模式的环回版本,并根据数据模式和数据模式的环回版本计算误码率。

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