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LINER AND CAP STRUCTURES FOR REDUCING LOCAL INTERCONNECT VERTICAL RESISTANCE WITHOUT COMPROMISING RELIABILITY

机译:减少局部互连垂直电阻而又不降低可靠性的衬里和帽盖结构

摘要

Embodiments of the invention are directed to an interconnect stack including a first dielectric layer, a first trench formed in the first dielectric layer, and a first liner deposited in the first trench, wherein the first liner defines a second trench. A first conductive material is in the second trench and deposited over the first dielectric layer and the first conductive material. A third trench extends through the second dielectric layer and is over the first conductive material. A bottom surface of the third trench includes at least a portion of the top surface of the first conductive material. A second liner is in the third trench, on sidewalls of the third trench, and also on the portion of the top surface of the first conductive material. The second liner functions as a cap region configured to counter electro-migration or surface migration of the first conductive material.
机译:本发明的实施例针对一种互连堆叠,该互连堆叠包括第一介电层,形成在第一介电层中的第一沟槽以及沉积在第一沟槽中的第一衬垫,其中第一衬垫限定第二沟槽。第一导电材料在第二沟槽中并沉积在第一介电层和第一导电材料上方。第三沟槽延伸穿过第二电介质层并且在第一导电材料上方。第三沟槽的底表面包括第一导电材料的顶表面的至少一部分。第二衬垫在第三沟槽中,在第三沟槽的侧壁上以及在第一导电材料的顶表面的一部分上。第二衬层用作被配置为抵抗第一导电材料的电迁移或表面迁移的盖区域。

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