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Liner and cap structures for reducing local interconnect vertical resistance without compromising reliability

机译:衬里和盖结构,用于减少局部互连垂直电阻而不会影响可靠性

摘要

Embodiments of the invention are directed to an interconnect stack including a first dielectric layer, a first trench formed in the first dielectric layer, and a first liner deposited in the first trench, wherein the first liner defines a second trench. A first conductive material is in the second trench and deposited over the first dielectric layer and the first conductive material. A third trench extends through the second dielectric layer and is over the first conductive material. A bottom surface of the third trench includes at least a portion of the top surface of the first conductive material. A second liner is in the third trench, on sidewalls of the third trench, and also on the portion of the top surface of the first conductive material. The second liner functions as a cap region configured to counter electro-migration or surface migration of the first conductive material.
机译:本发明的实施例涉及一种互连堆叠,其包括第一介电层,形成在第一介电层中的第一沟槽,以及沉积在第一沟槽中的第一衬垫,其中第一衬里限定了第二沟槽。 第一导电材料位于第二沟槽中并沉积在第一介电层和第一导电材料上。 第三沟槽延伸穿过第二电介质层,并且是第一导电材料。 第三沟槽的底表面包括第一导电材料的顶表面的至少一部分。 第二衬里位于第三沟槽的侧壁上的第三沟槽中,并且还在第一导电材料的顶表面的部分上。 第二衬垫用作配置成对第一导电材料的电迁移或表面迁移的帽区域。

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