ESD PROTECTION CIRCUIT WITH REDUCED PARASITE CAPACITANCE AND METHOD FOR REDUCING ESD PARASITE CAPACITANCE

摘要

An ESD protection circuit includes at least two unidirectional conduction units arranged between an IO node of an integrated circuit and a positive voltage node, where a first connection node is between the at least two unidirectional conduction units; at least two unidirectional conduction units arranged between the IO node and a negative voltage node, where a second connection node is between the at least two unidirectional conduction units; and a voltage tracking circuit. The input of the voltage tracking circuit is electrically connected to the IO node and the output of the voltage tracking circuit is electrically connected to at least one of the first connection end and the second connection end. By reducing the voltage difference between the IO node and the first connection end or between the IO node and the second connection end, the parasite capacitance associated with the unidirectional conduction unit can be reduced.