首页> 外国专利> STACKED INTEGRATION OF lll-N TRANSISTORS AND THIN-FILM TRANSISTORS

STACKED INTEGRATION OF lll-N TRANSISTORS AND THIN-FILM TRANSISTORS

机译:lll-N晶体管和薄膜晶体管的堆叠集成

摘要

Disclosed herein are IC structures, packages, and devices that include thin-film transistors (TFTs) integrated on the same substrate/die/chip as III-N transistors. An example IC structure includes an III-N transistor provided in a first layer over a support structure (e.g., a substrate), and a TFT provided in a second layer over the support structure. The second layer is above the first layer, and, therefore, the III-N transistor and the TFT are “stacked” transistors. This way, one or more III-N transistors may be integrated with one or more TFTs, enabling monolithic integration of PMOS transistors, provided by TFTs, on a single chip with III-N NMOS transistors. Such integration may reduce costs and improve performance, e.g., by reducing RF losses incurred when power is routed off chip in a multi-chip package. Stacked arrangement of III-N transistors and TFTs provides a further advantage of reducing the total surface area occupied by these transistors.
机译:本文公开了包括与III-N晶体管集成在同一衬底/管芯/芯片上的薄膜晶体管(TFT)的IC结构,封装和器件。示例IC结构包括设置在支撑结构(例如,基板)上方的第一层中的III-N晶体管和设置在支撑结构上方的第二层中的TFT。第二层在第一层之上,因此III-N晶体管和TFT是“堆叠”晶体管。这样,一个或多个III-N晶体管可以与一个或多个TFT集成,从而能够将由TFT提供的PMOS晶体管与III-N NMOS晶体管单片集成。这种集成可以例如通过减少在多芯片封装中的芯片外路由电源时引起的RF损耗来降低成本并提高性能。 III-N晶体管和TFT的堆叠布置提供了减小这些晶体管所占据的总表面积的另一优点。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号