Asymmetrical T-coil design for high-speed transmitter IO ESD circuit applications

摘要

For a T-coil IC, a first inductor core is on an M_x layer, has at least 1⅜ turns, and has a first-inductor-core-first end and a first-inductor-core-second end. A second inductor core is on an M_x-1 layer, has at least 2⅝ turns, and has a second-inductor-core-first end and a second-inductor-core-second end. The first-inductor-core-second end is connected to the second-inductor-core-first end at a node. A third inductor core is on an M_x-2 layer and has at least 3 turns. The third inductor core has a third-inductor-core-first end and a third-inductor-core-second end. The second-inductor-core-second end is connected to the third-inductor-core-first end. A tap is on an M_x-3-y layer, where y≥0. The tap is connected to the first and second inductor cores at the node. A first inductor is formed by the first inductor core, and a second inductor is formed by the second and third inductor cores.