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LOW-CAPACITANCE ELECTRO-STATIC-DISCHARGE (ESD) PROTECTION STRUCTURE WITH TWO FLOATING WELLS
LOW-CAPACITANCE ELECTRO-STATIC-DISCHARGE (ESD) PROTECTION STRUCTURE WITH TWO FLOATING WELLS
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机译:具有两个浮井的低电容静电放电(ESD)保护结构
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摘要
An Electro-Static-Discharge (ESD) input-protection device has an NPNP structure of a N+ cathode formed in a FINFET fin or highly-doped region over a floating P-well, and a P+ fin or highly-doped region anode formed over a floating N-well that touches the floating P-well. The floating P-well is surrounded by an isolating N-well and has a deep N-well underneath to completely isolate the floating P-well from the p-type substrate. No well taps are formed in the floating wells or in the isolating N-wells. The floating P-well and the floating N-well are thus truly floating at all times. Since the wells are floating, the NPNP structure appears as three junction diodes in series, which has a lower capacitance than a single diode that the NPNP structure would appear as when one of the wells was shorted or biased. During an ESD event the NPNP structure behaves as a single diode.
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