WAFER LEVEL TESTING STRUCTURE FOR MULTI-SITES SOLUTION

摘要

The present invention provides a wafer level multi-site testing structure, including: a printed circuit board; at least two socket assemblies set side by side on the printed circuit board, wherein each socket assembly includes a socket base plate and a positioning stiffener to form a socket; at least two sub circuit board assemblies of which any one is installed within the socket to be removable, and each of which includes a sub circuit board and a final testing substrate; a fixating ring set on the printed circuit board and provided with a hollow portion, wherein the socket assembly and the sub circuit board assembly are positioned within the hollow portion; and a probe head assembly set above the sub circuit board assembly and fixated on the fixing ring. The present invention arranges a plurality of final testing substrates side by side according to positions to concurrently perform a wafer testing process at multi-sites, thereby improving testing efficiency, and also can be designed in a plug manner to provide convenient replacement and testing effects.