BURIED CHANNEL ARRAY TRANSISTOR HAVING IMPROVED LEAKAGE CURRENT CHARACTERISTICS

摘要

The present invention relates to a buried channel array transistor including: a silicon substrate (100) where a drain (130) and a source (140) are respectively formed in predetermined regions; and a gate (110) buried in the silicon substrate (100) between the drain (130) region and the source (140) region. The upper surface of the gate (110) is buried so as to be positioned below the upper surface of the silicon substrate (100). An insulator (150) is buried in the drain (130) region or the source region (140). Value (x/y) obtained by dividing the distance (x) between the upper surface of the silicon substrate (100) and the upper surface of the insulator (150) buried in the silicon substrate (100) by the distance (y) between the upper surface of the silicon substrate (100) and the upper surface of the gate (110) buried in the silicon substrate (100) is 0.6 or more and 1.0 or less.;COPYRIGHT KIPO 2020