ON-CHIP NOISE REDUCTION OR REDUCTION OF SUPPLY VOLTAGE USING LOCAL DETECTION LOOPES IN A PROCESSOR CORE

摘要

Techniques are provided to enable on-chip noise reduction and / or supply voltage reduction using local detection loops in a processor core. In one example, a method implemented by a computer can have a detection, by a processor core, of a voltage dip on a first region of the processor core. The method implemented by a computer can also include transmitting, through the processor core, voltage dip information to a local controller located in the first area and to a global controller located in the processor core. Furthermore, the method implemented by a computer may include applying, by the processor core, a first mitigation measure to the first area of the processor core in response to a local instruction received from the local controller. The local instruction may include an indication of the first mitigation measure.